Typically, the gate electrode of complimentary MOSFETs has been formed by patterning a layer of polysilicon after doping thereof by ion implantation and/or solid-phase diffusion of N-type impurities, such as phosphorous or arsenic. Typically, the gate electrode will be disposed over two separate regions, a P-type region and an N-type region. The P-type region is utilized to form N-channel transistors and the N-type region is utilized to form P-channel transistors. These are typically referred to as a P-tank and an N-tank. In this prior art system, the gate electrodes for both the N-channel transistors and the P-channel transistors are of N-type with the source/drain regions in the N-channel transistor being N-type and the source/drain regions in the P-channel devices being P-type.
As the channel regions decrease in width as a result of the finer photolithography techniques and processes that are currently in use, the gate electrode for the P-channel transistor have been doped with a P-type impurity in order to suppress the short channel effect. In order to accomplish this, it is necessary to dope the polysilicon layer from which the gate electrodes are formed with both N-type impurities and P-type impurities. One system that has been proposed for achieving this is to utilize some type of mask and dope N-type impurities in the portion of the polysilicon layer overlying the P-type tank and then masking off this portion of the substrate and exposing the portion of the polysilicon layer overlying the N-tank and doping it with P-type impurities. Thereafter, the gate is patterned in the poly layer and underlying gate oxide layer and source/drain implants formed on either side of the gate in both the P-tank and the N-tank. In some cases, the source/drain implants and the implants into the gate electrodes are performed at the same time. In another technique for doping the gate electrodes for both transistors provides for some type of diffusion barrier between the gate electrodes for the N-channel and P-channel transistors, especially when the gate electrodes are formed from a common strip of polysilicon. This barrier can be formed from some type of nitride such as a metal nitride layer. However, the step of initially providing the N-doped and P-doped regions of polysilicon to form the gate electrodes for the N-channel and P-channel transistors requires a number of different steps. This can create a problem due to the additional thermal cycles that are required.